The present invention relates generally to a gate turn-off thyristor (hereinafter referred to as GTO thyristor). In particular, the invention relates to a multi-emitter type GTO thyristor suitable for control of a large current.
A GTO thyristor is a semiconductor switching control device which is constructed of a semiconductor substrate of pnpn 4-layer structure with intervening junctions, a pair of main electrodes ohmic-contacted to the outer layers of the substrate, and a gate electrode ohmic-contacted to one inner layer of the substrate, and whereby a current path between the main electrodes is switched, upon reception of a gate signal applied to the gate electrode, into a turn-on (turn-off) state from a turn-off (turn-on) state. A main technical theme of GTO thyristors is to turn off a large current at high speed with as small a gate current as possible. To solve this problem, various schemes have been proposed.
One known example is a so-called multi-emitter type GTO thyristor having the outer n layer (cathode-emitter layer) composed of a plurality of strip-like regions each having a width of 0.2 to 0.4 mm and a length of several milimeters, as shown in FIG. 1 of U.S. Pat. No. 4,500,903 and FIGS. 3 and 8 of U.S. Pat. No. 4,542,398. The gate electrodes of a GTO thyristor of this type is formed surrounding each strip-like region with a constant space therefrom. With such an arrangement, it is possible during a turn-off operation to remove carriers from the inner p layer (p base layer) adjacent to each strip-like region, uniformly over the entirety of the cathode-emitter layer and at high speed.
Another example of a GTO thyristor having an anode-emitter layer of so-called shorted emitter structure wherein the inner n layer (n base layer) and the outer p layer (anode-emitter layer) are contacted to the anode electrode, as shown in U.S. Pat. No. 3,239,728. With such arrangement, removal of carriers during a turn-off operation can be effected not only from the gate electrode but also from the anode side, thereby improving the speed of a turn-off operation. As to the shorted structure of the anode-emitter layer, it is also known, as shown in U.S. Pat. No. 4,450,467 and U.S. Pat. No. 4,500,903, that n.sup.+ regions having a higher impurity concentration than that of the n base layer are formed between the n base layer and the anode electrode. These n.sup.+ regions help to remove carriers from the n base layer more rapidly.
As shown in FIGS. 1 and 2 of U.S. Pat. No. 4,500,903, a typical GTO thyristor employs both the cathode-emitter layer structure composed of a plurality of strip-like regions, and a shorted emitter structure of the anode-emitter layer, thereby realizing an improved turn-off performance. A problem associated with such a GTO thyristor is that of a large current capacity is required, a large number of strip-like regions constituting the cathode-emitter layer must be provided forming a multi-ring configuration as shown in U.S. Pat. No. 4,500,903 so that turn-off times may become non-uniform. This non-uniformity in the turn-off time will be discussed with reference to FIGS. 1 to 3.
In FIGS. 1 to 3, a semiconductor substrate 1 of disc shape comprises a cathode-emitter layer N.sub.E composed of a plurality of strip-like regions 13 adjacent to one main surface 11, a P base layer P.sub.B adjacent to the cathode-emitter layer N.sub.E and the main surface 11, an N base layer N.sub.B adjacent to the P base layer P.sub.B, an anode-emitter layer P.sub.E adjacent to the N base layer N.sub.B and to another main surface 12, and an N.sup.+ layer of n-type impurity concentration higher than that of the N base layer N.sub.B adjacent to the N base layer N.sub.B, anode-emitter layer and the main surface 12. Each strip-like region 13 is radially and concentrically arranged in the semiconductor substate to form a double ring configuration as a whole. The anode-emitter layer P.sub.E is composed of a plurality of strip-like regions 14. The strip-like regions 14 are disposed such that when each strip-like region 13 of the cathode-emitter layer N.sub.E is orthogonally projected upon the main surface 12, the projected strip-like region 13 overlays upon two strip-like regions 14 with their longitudinal directions aligned with each other. The N.sup.+ layer of n-type high impurity concentration is thicker than the anode-emitter layer P.sub.E and occupies all the regions where the strip-like regions 14 are not present on the main surface 12. A cathode electrode 2 is ohmic-contacted to the strip-like region 13 on the main surface 11, whereas an anode electrode 3 is ohmic-contacted to the whole area of the main surface 12. A gate electrode 4 is ohmic-contacted to the exposed surface of the P base layer P.sub.B on the main surface 11 to surround the strip-like region 13 with a constant space therefrom. The plane of the gate electrode 4 formed on the main surface 11 is disposed nearer to the main surface 12 than the plane of the cathode electrode 2. A gate terminal 5 constitutes a gate signal input area.
The dimensions of unit GTO thyristors each having one strip-like region 13 as its outer layer are the same, irrespective of the inner and outer positions of the two rings. Particularly, irrespective of the inner (FIG. 2) and outer (FIG. 3) positions of the two rings, the length l l, width w and distance d between two strip-like regions 14 are the same.
With the GTO thyristor constructed as above, the distances from the gate signal input area 5 to the strip-like regions 13 at the inner and outer positions of the two rings differ more than a length of the strip-like region 13. Thus, the tranverse resistance of the gate electrode 4 for a unit GTO thyristor G2 at the outer ring is larger than that of a unit GTO thyristor G1 at the inner ring. Therefore, a reverse bias voltage (gate signal voltage) applied between the gate electrode 4 and the cathode electrode 2 of the unit GTO thyristor G2 at the outer ring is reduced by a greater amount than that applied to the unit GTO thyristor G1 at the inner ring, thereby lengthening the turn-off time of the unit thyristor at G2 during a turn-off operation.
Consequently, during a turn-off operation of a GTO thyristor, the unit GTO thyristors G1 at the inner position of the two rings turn off first wherein conduction current is then concentrated on the unit GTO thyristors G2 at the outer position which still remain on, thereby resulting in thermal breakdown of the unit GTO thyristors G2.